Getting started with Xilinx XC3S200 /SX3S400 PFGAs

iMPACT is part of the free available ISE Webpack.

The version used here is ISE WebPack 8.1i.
The same applies to ISE WebPack 8.2i.

• 1. Install Xilinx ISE WebPack 8.1i and 8.2i (Windows / Linux)

• 2. Configure FPGA Device without Flash

• 3. Generate PROM File for automatic FPGA configuration with Flash after power up and reset

1. Install Xilinx ISE WebPack 8.1i and 8.2i (Windows / Linux)

• Download Xilinx ISE WebPack 8.1i

• for Windows:

  • execute WebPACK_81i_SFD.exe
    

• for Linux:

  • NOTE: ISE WebPack must be installed as root!
    >su root

  • download WebPACK_81i_SFD.sh

  • make the shell scipt executable
    >chmod u+x WebPACK_81i_SFD.sh

  • install ISE WebPack as root
    >./WebPACK_81i_SFD.sh

  • make settings.sh runnable
    >chmod u+x settings.sh 

  • set environment variables with
    >source settings.sh  (or >source settings.csh)

  • run project navigator:
    >ise

2. Configure XILINX FPGA Device without Flash:

Notice: In this mode the FPGA keeps configuration until reset or next power up sequence.

• Start iMPACT.

• Attach Xilinx JTAG Parallel Cable III to the parallel port.
  Check correct detection under 'Output / Cable setup'.

• Select Boundary Scan Mode from the right selection 'iMPACT Modes' if not already done.

• Execute 'File / Initialize Chain' to detect the devices in the daisy chain.
  

• Select the configuration bit stream to configure FPGA with the context menu (right button) 'Assign New Configuration File'.

3. Generate PROM File for automatic FPGA configuration with Flash after power up and reset:

• Select PROM File Formatter from the right iMPACT Modes.

• Select Edit / Launch Wizard.

• Choose Xilinx PROM and PROM File Name.

• Select XCF02S Flash and use 'Add' buttom.

• Answer the question 'Would you like to add another device file' with No.

• Generate the PROM file with 'Operations / Generate File'.

• Now change in Boundary Scan mode.

• Now you can assign the newly created PROM file to the Flash.

• After updating the flash the FPGA loads the configuration bit stream from flash after power up or reset.

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